In the semiconductor industry, there is a continuing effort to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) on integrated circuits. In the electronics industry, packaging density has continuously increased to accommodate more electronic devices into one package. Three-dimensional (3D) stacking technology of wafers has been used to increase the device integration density in integrated circuits and the packaging density in 3D-electronic packaging system. A top layer of one wafer may be connected to a bottom layer of the other wafer through silicon interconnects or vias.
A through-silicon via (hereinafter “TSV”) is a vertical electrical connection passing completely through a silicon substrate, such as a wafer or a die. TSV technology is often used in 3D-packaging applications and 3D-integrated circuits, sometimes collectively referred to as “3D-stacking.” The TSV is formed by forming a vertical via through the substrate and filling the via with a conductive material, such as copper. A thinning process may then be conducted to remove a portion of the silicon substrate, such as by grinding, polishing (e.g., chemical-mechanical planarization), or a combination thereof, so that an end of the TSV protrudes above the silicon substrate. The copper-filled TSV may be used to form a vertical electrical connection between multiple substrates, such as semiconductor dice. However, conventional thinning processes have many drawbacks. For example, since the protrusion height of the TSV above the surrounding substrate surface is no more than a few hundred microns, it is difficult to achieve a consistent protrusion height of the TSVs using grinding or polishing processes. This process limitation results in 3D-stacking with inferior performance, especially when there are multiple TSVs protruding above the substrate surface. As an alternative to abrasive techniques used to expose TSV ends and for better process control, conventional etch chemistries may be used to remove silicon from a back surface of a substrate to expose a TSV end. The etch chemistry may include a wet etching process using potassium hydroxide (KOH), ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH), or a dry etching process using HBr/O2, CF4 or NF3. However, such etch processes are slow, and are not selective to oxides used as a liner for copper-filled TSVs. In addition, while bias RF power may be used to speed up the etch rate, the etch rate is still undesirably slow, and a detrimental byproduct of such an approach is microtrenching of the substrate material along any exposed features. While a sulfur hexafluoride (SF6)-containing etchant may be used to remove a portion of the substrate bearing TSVs at a much faster (e.g., eight times faster) rate than other etch chemistries, and SF6 is highly selective to the oxide, sulfur in the SF6-containing etchant reacts with copper of the TSV, producing copper sulfide on the copper-filled TSV in the form of a “copper sulfide balloon.” The copper sulfide is corrosive and erodes exposed copper. The copper sulfide is also difficult to remove and negatively impacts 3D-stacking connectivity of multiple semiconductor substrates if not thoroughly removed.